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Address code generation for DSP instruction-set architectures., и . ACM Trans. Design Autom. Electr. Syst., 8 (3): 384-395 (2003)Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors., и . VTC Spring, стр. 1-5. IEEE, (2013)Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies., , , и . ICCD, стр. 519-524. IEEE Computer Society, (2000)Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors., , и . ICECS, стр. 77-80. IEEE, (2018)Efficient Implementation of Multiple Interleavers in IDMA for 5G., и . ISOCC, стр. 119-120. IEEE, (2018)Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000., и . ICIP, стр. 2665-2668. IEEE, (2009)Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software., , , , и . DAC, стр. 939-944. ACM Press, (1999)An O(n3logn)-Heuristic for Microcode Bit Optimization., , и . ICCAD, стр. 180-183. IEEE Computer Society, (1990)Verification methodology of compatible microprocessors., , , , , , , , , и 2 other автор(ы). ASP-DAC, стр. 173-180. IEEE, (1997)Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation., , и . ICCAD, стр. 138-141. IEEE Computer Society / ACM, (2003)