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Disambiguation of "Ranganathan, N."

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Peak Power Minimization Through Datapath Scheduling.

, , and . ISVLSI, page 121-126. IEEE Computer Society, (2003)

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Hiranmayi Ranganathan

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N -L N Nguyen

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Other publications of authors with the same name

Power estimation of sequential circuits using hierarchical colored hardware petri net modeling., and . ISLPED, page 267-270. ACM, (2002)ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation., and . VLSI Design, page 291-296. IEEE Computer Society, (1994)Simultaneous peak and average power minimization during datapath scheduling for DSP processors., , and . ACM Great Lakes Symposium on VLSI, page 215-220. ACM, (2003)PANTHER: a parallel neuro-systolic architecture for real-time processing., and . ICNN, page 1006-1011. IEEE, (1996)trulla : An Algorithm For Path Planning Among Weighted Regions By Localized Propagations., , and . IROS, page 469-476. IEEE, (1992)Enhancing arithmetic and tree-based coding., , and . Inf. Process. Manag., 25 (3): 293-305 (1989)Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis., and . VLSI Design, page 670-. IEEE Computer Society, (2004)SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division., , and . VLSI Design, page 25-30. IEEE Computer Society, (1993)Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach., , and . VLSI Design, page 230-233. IEEE Computer Society, (1998)VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis., , and . IPPS, page 700-704. IEEE Computer Society, (1993)