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An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems.

, , , , and . ICRC, page 1-2. IEEE, (2017)

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Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper)., , and . IJCNN, page 4557-4563. IEEE, (2017)Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue)., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 205-207 (2011)Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array., , and . Communications in Computing, page 167-176. CSREA Press, (2004)Design of ultra high density and low power computational blocks using nano-magnets., , , and . ISQED, page 223-230. IEEE, (2013)A novel low-complexity method for parallel multiplierless implementation of digital FIR filters., and . ISCAS (3), page 2020-2023. IEEE, (2005)Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure., , , , and . ISSCC, page 400-611. IEEE, (2007)Spin based neuron-synapse module for ultra low power programmable computational networks., , , and . IJCNN, page 1-7. IEEE, (2012)A logic-aware layout methodology to enhance the noise immunity of domino circuits., and . ISCAS (5), page 637-640. IEEE, (2003)On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs.. ISCAS, page 1623-1626. IEEE, (1993)VLSI Signal Processing in FPGAs., , and . VLSI Design, page 609. IEEE Computer Society, (1999)