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Analysis of compressor architectures in MOS current-mode logic., and . ICECS, page 13-16. IEEE, (2010)Experimental Comparison Between SBC and FPGA for Embedded Neural Network Acceleration., , , and . ICC, page 6078-6083. IEEE, (2023)An Improved Algorithm for Boolean Factoring.. ISCAS, page 241-244. IEEE, (1994)Optimum design of two-level MCML gates., and . ICECS, page 141-144. IEEE, (2008)A reparameterization and monitoring platform for energy efficient GPS trackers in behavioural analysis of wildlife., , , and . CITS, page 1-6. IEEE, (2023)TDEC metric for 50G-PON using Optical Amplification., , , , , , , and . ICTON, page 1-4. IEEE, (2023)Relation Between TDEC, Extinction Ratio and Chromatic Dispersion in 50G PON., , , and . CSNDSP, page 555-557. IEEE, (2022)Study of TDEC for 50G-PON Upstream at 50 Gb/s in Negative Dispersion Regime using 25G-class Transceivers., , , , and . OFC, page 1-3. IEEE, (2023)Design of MOS current mode logic gates - computing the limits of voltage swing and bias current.. ISCAS (6), page 5637-5640. IEEE, (2005)A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates.. IEICE Electron. Express, 10 (17): 20130599 (2013)