Author of the publication

A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS.

, , , , , , and . ESSCIRC, page 471-474. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

High-Power 150/245-GHz Fundamental Oscillators With 12.1/-2.54-dBm Peak Output Power for Phased Array Transceivers., , , , , and . IEEE J. Solid State Circuits, 59 (11): 3683-3693 (November 2024)A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core., , , , and . IEEE Access, (2021)A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS., , , , , , and . ESSCIRC, page 471-474. IEEE, (2021)A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core., , , and . ASP-DAC, page 301-302. IEEE, (2018)Design of High-Gain Sub-THz Regenerative Amplifiers Based on Double-Gmax Gain Boosting Technique., , , , , and . IEEE J. Solid State Circuits, 56 (11): 3388-3398 (2021)A 293/440 GHz Push-Push Double Feedback Oscillators with 5.0/-3.9 dBm Output Power and 2.9/0.6 % DC-to-RF Efficiency in 65 nm CMOS., , , and . VLSI Circuits, page 1-2. IEEE, (2020)A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing., , , , , and . A-SSCC, page 149-152. IEEE, (2017)A 230-260-GHz Wideband and High-Gain Amplifier in 65-nm CMOS Based on Dual-Peak $G_max$ -Core., , , , and . IEEE J. Solid State Circuits, 54 (6): 1613-1623 (2019)H-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized Gmax-Core and Transmission Line-Based Zero-Degree Power Combining Networks., , and . IEEE J. Solid State Circuits, 58 (11): 3089-3102 (November 2023)