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Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien.

, and . GI Jahrestagung (1), volume P-67 of LNI, page 339-343. GI, (2005)

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Synchronization Fault Cryptanalysis for Breaking A5/1., , , and . WEA, volume 3503 of Lecture Notes in Computer Science, page 415-427. Springer, (2005)Flip-Flops and Scan-Path Elements for Nanoelectronics., and . DDECS, page 307-312. IEEE Computer Society, (2007)Hardware/Software Based Hierarchical Self Test for SoCs., , , , , and . DDECS, page 159-160. IEEE Computer Society, (2006)A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features., , and . IOLTS, page 241-246. IEEE Computer Society, (2005)Migrating Electronic Systems from Fault Tolerant Computing to Error Resilience.. SPA, page 13. IEEE, (2018)Iterative error correction with double/triple error detection., and . SPA, page 14-19. IEEE, (2016)An efficient on-line-test and back-up scheme for embedded processors., , and . ITC, page 964-972. IEEE Computer Society, (1999)Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration., , and . ARCS Workshops, volume P-200 of LNI, page 251-262. GI, (2012)RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems., , , , , , , , , and 8 other author(s). CoRR, (2019)Gate delay fault test generation for non-scan circuits., , , and . ED&TC, page 308-313. IEEE Computer Society, (1995)