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Microarchitecture evaluation with floorplanning and interconnect pipelining.

, , , , , , , и . ASP-DAC, стр. 8-15. ACM Press, (2005)

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Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

 

Другие публикации лиц с тем же именем

Multilevel floorplanning/placement for large-scale modules using B*-trees., , , и . DAC, стр. 812-817. ACM, (2003)Constrained "Modern" Floorplanning., , и . ISPD, стр. 128-135. ACM, (2003)Faster and more accurate wiring evaluation in interconnect-centric floorplanning., , , и . ACM Great Lakes Symposium on VLSI, стр. 62-67. ACM, (2001)Integrating dynamic thermal via planning with 3D floorplanning algorithm., , , , , , , и . ISPD, стр. 178-185. ACM, (2006)Slicing floorplans with boundary constraints., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1385-1389 (1999)Slicing floorplans with range constraint., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (2): 272-278 (2000)Integrated floorplanning and interconnect planning., , , , , и . ICCAD, стр. 354-357. IEEE Computer Society, (1999)Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach., и . Encyclopedia of Algorithms, Springer, (2008)A Theoretical Upper Bound for IP-Based Floorplanning., , , и . COCOON, том 3595 из Lecture Notes in Computer Science, стр. 411-419. Springer, (2005)Microarchitecture evaluation with floorplanning and interconnect pipelining., , , , , , , и . ASP-DAC, стр. 8-15. ACM Press, (2005)