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A global interconnect optimization algorithm under accurate delay model using solution space smoothing.

Y. Cai, Y. Wang, and X. Hong. ISCAS (1), page 93-96. IEEE, (2005)

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Yongjie Cai

Cai Berg

Lijun Cai

Xuediao Cai

Cuifang Cai

Other publications of authors with the same name

Leakage power optimization for clock network using dual-Vth technology.W. Shen, Y. Cai, and X. Hong. ISCAS, page 2769-2772. IEEE, (2008)A novel fine-grain track routing approach for routability and crosstalk optimization.Z. Qi, Q. Zhou, Y. Jia, Y. Cai, Z. Li, and H. Yao. ISQED, page 621-626. IEEE, (2011)A new splitting graph construction algorithm for SIAR router.J. Zhao, H. Yao, Y. Cai, and Q. Zhou. ASICON, page 1-4. IEEE, (2013)SIAR: splitting-graph-based interactive analog router.F. Yang, H. Yao, Q. Zhou, and Y. Cai. ACM Great Lakes Symposium on VLSI, page 367-370. ACM, (2011)Evaluating a bounded slice-line grid assignment in O(nlogn) time.S. Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C. Cheng, and J. Gu. ISCAS (4), page 708-711. IEEE, (2003)SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips.Q. Wang, W. He, H. Yao, T. Ho, and Y. Cai. ISPD, page 49-56. ACM, (2015)Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.B. Liu, Y. Cai, Q. Zhou, and X. Hong. ASP-DAC, page 582-587. IEEE, (2006)Efficient model reduction of interconnects via double gramians approximation.B. Yan, S. Tan, G. Chen, and Y. Cai. ASP-DAC, page 25-30. IEEE, (2010)Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding.X. Wang, Q. Zhou, Y. Cai, and G. Qu. Integr., (2019)Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods.X. Wang, Q. Zhou, Y. Cai, and G. Qu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1844-1857 (2019)

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Disambiguation of "Cai, Yici"

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A global interconnect optimization algorithm under accurate delay model using solution space smoothing.

Please choose a person to relate this publication to

Yongjie Cai

Cai Berg

Lijun Cai

Xuediao Cai

Cuifang Cai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cai, Yici"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A global interconnect optimization algorithm under accurate delay model using solution space smoothing.

Please choose a person to relate this publication to

Yongjie Cai

Cai Berg

Lijun Cai

Xuediao Cai

Cuifang Cai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A global interconnect optimization algorithm under accurate delay model using solution space smoothing.