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Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation.

, and . CYSARM@CCS, page 1-12. ACM, (2020)

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An Asynchronous Interconnect Architecture for Device Security Enhancement., and . VLSI Design, page 209-215. IEEE Computer Society, (2006)Architectural Contracts for Safe Speculation., , , , , , , , , and 3 other author(s). ICCD, page 578-586. IEEE, (2023)The CHERI capability model: Revisiting RISC in an age of risk., , , , , , , , , and . ISCA, page 457-468. IEEE Computer Society, (2014)Improving Smart Card Security Using Self-Timed Circuits., , , , and . ASYNC, page 211-218. IEEE Computer Society, (2002)Demystifying Data-Driven and Pausible Clocking Schemes., and . ASYNC, page 175-185. IEEE Computer Society, (2007)Implications of Rent's Rule for NoC Design and Its Fault-Tolerance., , , and . NOCS, page 283-294. IEEE Computer Society, (2007)Flow-aware allocation for on-chip networks., and . NOCS, page 183-192. IEEE Computer Society, (2009)A consistency checker for memory subsystem traces., , and . FMCAD, page 133-140. IEEE, (2016)Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits., , , , , and . PLoS Comput. Biol., (2010)Towards xBGAS on CHERI: Supporting a Secure Global Memory., , , , , and . IPDPS Workshops, page 578-581. IEEE, (2023)