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Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 238-246 (2017)Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor., , , , и . IEEE Trans. Computers, 60 (9): 1274-1287 (2011)AVF Analysis Acceleration via Hierarchical Fault Pruning., , , и . ETS, стр. 87-92. IEEE Computer Society, (2011)On Modeling Cross-Talk Faults., , , и . DATE, стр. 10490-10495. IEEE Computer Society, (2003)Novel approach to reduce power droop during scan-based logic BIST., , , , , и . ETS, стр. 1-6. IEEE Computer Society, (2013)Impact analysis of performance faults in modern microprocessors., , , , и . ICCD, стр. 91-96. IEEE Computer Society, (2009)A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit., , , и . DATE, стр. 1078-1083. IEEE Computer Society, (2004)Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller., , , , и . DFT, стр. 454-462. IEEE Computer Society, (2008)Estimating Error Propagation Probabilities with Bounded Variances., , и . DFT, стр. 41-49. IEEE Computer Society, (2007)Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller., , , , и . IEEE Trans. Computers, 60 (9): 1260-1273 (2011)