( en | de | ru )

 

Disambiguation of "Vasudevan, Shobha"

Author of the publication

copydeleteadd this publication to your clipboard
Learning Semantic Representations to Verify Hardware Designs.

, , , , , , and . NeurIPS, page 23491-23504. (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ramaswami Vasudevan

N Vasudevan

Desikachari Vasudevan

Anju Vasudevan

Ramaswami Vasudevan

 

Other publications of authors with the same name

Coverage closure in SoC verification: Are we chasing a mirage?. VTS, page 211. IEEE Computer Society, (2011)Using static analysis for coverage extraction fromemulation/prototyping platforms., , , , , and . CODES+ISSS, page 207-214. ACM, (2012)Learning Semantic Representations to Verify Hardware Designs., , , , , , and . NeurIPS, page 23491-23504. (2021)Automated Generation and Selection of Interpretable Features for Enterprise Security., , , and . IEEE BigData, page 1258-1265. IEEE, (2018)Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs., and . QEST, page 143-152. IEEE Computer Society, (2010)Word level feature discovery to enhance quality of assertion mining., , and . ICCAD, page 210-217. ACM, (2012)Efficient Microprocessor Verification using Antecedent Conditioned Slicing., , and . VLSI Design, page 43-49. IEEE Computer Society, (2007)Improved verification of hardware designs through antecedent conditioned slicing., , and . Int. J. Softw. Tools Technol. Transf., 9 (1): 89-101 (2007)Using automatically generated invariants for regression testing and bug localization., , , and . ASE, page 634-639. IEEE, (2013)Automatic decomposition for sequential equivalence checking of system level and RTL descriptions., , , and . MEMOCODE, page 71-80. IEEE Computer Society, (2006)