Author of the publication

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.

, , and . ICCD, page 23-28. IEEE Computer Society, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs., , , , and . ASP-DAC, page 170-175. ACM, (2021)ECBL: an extended corner block list with solution space including optimum placement., , , and . ISPD, page 150-155. ACM, (2001)An integrated floorplanning with an efficient buffer planning algorithm., , , , , , and . ISPD, page 136-142. ACM, (2003)Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications., , , and . DAC, page 166-171. ACM, (2009)Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List., , , , , and . DAC, page 770-775. ACM, (2001)Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond., and . ISPD, page 123-128. ACM, (2017)On the construction of zero-deficiency parallel prefix circuits with minimum depth., , and . ACM Trans. Design Autom. Electr. Syst., 11 (2): 387-409 (2006)On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design., and . ACM Great Lakes Symposium on VLSI, page 257-262. ACM, (2009)Adaptive sensitivity analysis with nonlinear power load modeling., , , and . SLIP@DAC, page 5:1-5:6. ACM, (2018)Network Partitioning into Tree Hierarchies., , and . DAC, page 477-482. ACM Press, (1996)