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A highly parallel Turbo Product Code decoder without interleaving resource., , , , and . SiPS, page 1-6. IEEE, (2008)FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems.. ERSA, page 9-18. CSREA Press, (2009)Efficient architecture for Reed Solomon block turbo code., , , , and . ISCAS, IEEE, (2006)Reed-Solomon behavioral virtual component for communication systems., , , , and . ISCAS (4), page 173-176. IEEE, (2004)Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis., , , and . ICECS, page 661-664. IEEE, (2018)Evaluation of the hardware complexity of the ADMM approach for LDPC decoding., , , , and . WCNC, page 1-6. IEEE, (2016)Comparison of different schedulings for the ADMM based LDPC decoding., , , , and . ISTC, page 51-55. IEEE, (2016)Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes., , , , and . SoftCOM, page 1-5. IEEE, (2017)Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis., , , and . SiPS, page 242-247. IEEE, (2019)Assertion support in high-level synthesis design flow., , , and . FDL, page 1-8. IEEE, (2011)