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UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration., , , , and . IEEE Trans. Computers, 62 (2): 225-241 (2013)A cosimulation methodology for HW/SW validation and performance estimation., , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 23:1-23:32 (2009)A testbench specification language for SystemC verification., and . CODES+ISSS, page 333-342. ACM, (2012)Correct-by-construction generation of device drivers based on RTL testbenches., , , and . DATE, page 1500-1505. IEEE, (2009)A time-window based approach for dynamic assertions mining on control signals., , and . VLSI-SoC, page 246-251. IEEE, (2015)On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms., and . VLSI-SoC (Selected Papers), volume 464 of IFIP Advances in Information and Communication Technology, page 110-128. Springer, (2014)Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level., , and . VLSI-SoC (Selected Papers), volume 661 of IFIP Advances in Information and Communication Technology, page 71-92. Springer, (2021)Logic-level analysis of high-level faults., and . ACM Great Lakes Symposium on VLSI, page 100-103. ACM, (2004)Exploiting assertions mining and fault analysis to guide RTL-level approximation., , , and . DATE, page 1-2. IEEE, (2023)On the Mutation Analysis of SystemC TLM-2.0 Standard., , and . MTV, page 32-37. IEEE Computer Society, (2009)