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Другие публикации лиц с тем же именем

A New Modulo (2n+1) Multiplier for IDEA., , и . Security and Management, стр. 318-324. CSREA Press, (2004)Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs., , , и . RACS, стр. 430-436. ACM, (2015)Cache leakage control mechanism for hard real-time systems., , , и . CASES, стр. 248-256. ACM, (2007)Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories., , и . RACS, стр. 243-248. ACM, (2018)Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs., , , и . DATE, стр. 1-6. European Design and Automation Association, (2014)PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support., , , , и . ASP-DAC, стр. 122-127. IEEE, (2022)SECRET: Selective error correction for refresh energy reduction in DRAMs., , , , и . ICCD, стр. 67-74. IEEE Computer Society, (2012)Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs., , и . ICCAD, стр. 458-465. ACM, (2012)Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories., , и . SAC, стр. 546-553. ACM, (2020)PM-COSYN: PE and memory co-synthesis for MPSoCs., , и . DATE, стр. 1590-1595. IEEE Computer Society, (2010)