( en | de | ru )

 

Disambiguation of "Pleskacz, Witold A."

Author of the publication

copydeleteadd this publication to your clipboard
DC/DC Buck Converter Soft-Start Methods.

, , and . MIXDES, page 131-135. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Witold Jeszke

Witold Lesniak

Witold Ostapowicz

Witold Zenk

Witold Slowinski

 

Other publications of authors with the same name

IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology., , and . MIXDES, page 334-338. IEEE, (2015)A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (2): 151-162 (1999)Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC., , , , , and . DSD, page 729-734. IEEE Computer Society, (2008)Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS., , and . DDECS, page 78-83. IEEE Computer Society, (2009)Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology., , , and . DDECS, page 259-262. IEEE Computer Society, (2008)LC-VCO design automation tool for nanometer CMOS technology., , and . DDECS, page 68-73. IEEE, (2012)PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications., , and . DDECS, page 29-34. IEEE Computer Society, (2011)The integrated transmitter and receiver modules for pulse oximeter system., , , , , , , and . MIXDES, page 243-248. IEEE, (2016)Yield Estimation of VLSI Circuits with Downscaled Layouts.. DFT, page 55-60. IEEE Computer Society, (1999)Design of a Wideband Low Noise Amplifier for a FMCW Synthetic Aperture Radar in 130 nm SiGe BiCMOS Technology., , , and . MIXDES, page 131-135. IEEE, (2018)