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Disambiguation of "Lee, Hyein"

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SchemaBoard: Supporting Correct Assembly of Schematic Circuits using Dynamic In-Situ Visualization.

, , , , , , , and . UIST, page 987-998. ACM, (2020)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Xavier Lee Lee

Bongsoo Lee

The role of negative regulators in coordination of the Myxococcus xanthus developmental program. Uni Marburg, (2009)

Min-Hi Lee

Induction and regulation of antiviral defence mechanisms through intracytoplasmic sensors. HU Berlin, (2009)

Hyemin Lee

Clara Lee

 

Other publications of authors with the same name

A Review on Benefits of IoT Integrated Blockchain based Supply Chain Management Implementations across Different Sectors with Case Study., , , , and . ICACT, page 138-141. IEEE, (2019)MAScreen: Augmenting Speech with Visual Cues of Lip Motions, Facial Expressions, and Text Using a Wearable Display., , and . SIGGRAPH ASIA Emerging Technologies, page 2:1-2:2. ACM, (2020)VirtualComponent: A Mixed-Reality Tool for Designing and Tuning Breadboarded Circuits., , , , and . CHI, page 177. ACM, (2019)Horizontal benchmark extension for improved assessment of physical CAD research., , and . ACM Great Lakes Symposium on VLSI, page 27-32. ACM, (2014)A New MIMO Signal Constellation for Secrecy and Performance Enhancing., , and . ICTC, page 924-928. IEEE, (2020)Evaluation of physical-layer security schemes for space-time block coding under imperfect channel estimation., , and . APCC, page 580-585. IEEE, (2022)Learning-based approximation of interconnect delay and slew in signoff timing tools., , , , and . SLIP, page 1-8. IEEE Computer Society, (2013)SchemaBoard: Supporting Correct Assembly of Schematic Circuits using Dynamic In-Situ Visualization., , , , , , , and . UIST, page 987-998. ACM, (2020)Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes., , , , , and . DAC, page 51:1-51:6. ACM, (2017)Minimum implant area-aware gate sizing and placement., and . ACM Great Lakes Symposium on VLSI, page 57-62. ACM, (2014)