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Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Impact of interconnects enhancement on SRAM design beyond 5nm technology node., , , and . ISCAS, page 1-5. IEEE, (2023)Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications., , , , , , and . ISCAS, page 1-5. IEEE, (2023)Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter., , , , , , , , , and 1 other author(s). OFC/NFOEC, page 1-3. IEEE, (2013)Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS., , , , , , , and . IEEE J. Solid State Circuits, 45 (6): 1198-1208 (2010)Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue.. ISPD, page 89. ACM, (2016)Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers., , , and . VTC Spring, page 3135-3139. IEEE, (2007)Human++: autonomous wireless sensors for body area networks., , , , , and . CICC, page 13-19. IEEE, (2005)A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 368-377. IEEE, (2006)Holisitic device exploration for 7nm node., , , , , , , , , and 5 other author(s). CICC, page 1-5. IEEE, (2015)