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Analog VLSI for robot path planning., , , and . J. VLSI Signal Process., 8 (1): 61-73 (1994)Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model., , , , and . IEEE Trans. Computers, 57 (9): 1277-1288 (2008)Using Intradisk Parallelism to Build Energy-Efficient Storage Systems., , and . IEEE Micro, 29 (1): 50-61 (2009)Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems., , , , and . J. Signal Process. Syst., 88 (2): 167-184 (2017)A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs., , , , and . ISQED, page 341-346. IEEE, (2018)Graphene Devices, Interconnect and Circuits - Challenges and Opportunities., , , and . ISCAS, page 69-72. IEEE, (2009)Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization., , , , and . DAC, page 126:1-126:6. ACM, (2014)A new taxonomy for reconfigurable prefix adders., and . ISCAS, page 1227-1230. IEEE, (2012)FlashPower: A detailed power model for NAND flash memory., , and . DATE, page 502-507. IEEE Computer Society, (2010)A Case for Thermal-Aware Floorplanning at the Microarchitectural Level., , , and . J. Instruction-Level Parallelism, (2005)