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Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC., , and . ICASSP (5), page 9-12. IEEE, (2004)Parallel global elimination algorithm and architecture design for fast block matching motion estimation., , and . ICASSP (5), page 153-156. IEEE, (2004)Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor., , , and . EMBC, page 7091-7094. IEEE, (2011)Memory efficient JPEG2000 architecture with stripe pipeline scheme., , , , and . ICASSP (5), page 1-4. IEEE, (2005)Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System., , , , and . ICASSP (2), page 97-100. IEEE, (2007)Line Buffer Wordlength Analysis for Line-Based 2-D DWT., , , and . ICASSP (3), page 924-927. IEEE, (2006)A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm., , , , and . ASP-DAC, page 145-150. IEEE, (1998)A hardware-oriented design for weighted median filters., , and . ASP-DAC, ACM, (1995)Design and implementation of JPEG encoder IP core., , , and . ASP-DAC, page 29-30. ACM, (2001)Region-of-unpredictable determination for accelerated full-frame feature generation in video sequences., , and . VCIP, page 434-437. IEEE, (2014)