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A tool for automatic design of analog circuits based on gm/ID methodology., , and . ISCAS, IEEE, (2006)A DC offset and CMRR analysis in a CMOS 0.35 µm operational transconductance amplifier using Pelgrom's area/accuracy tradeoff., and . Microelectron. J., 40 (9): 1281-1292 (2009)A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders., , , , , and . IEEE Trans. Circuits Syst. Video Technol., 30 (10): 3814-3828 (2020)A low-cost and high efficiency entropy encoder architecture for H.264/AVC., , , , and . VLSI-SoC, page 117-122. IEEE, (2012)Quality and Complexity Assessment of Learning-Based Image Compression Solutions., , , and . ICIP, page 599-603. IEEE, (2021)Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (12): 3126-3137 (2017)AxPPA: Approximate Parallel Prefix Adders., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 17-28 (2023)Algorithm and hardware design of a fast intra-frame mode decision module for h.264/AVC encoders., , , , , and . SBCCI, page 143-148. ACM, (2011)A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis., , and . SBCCI, page 239-244. ACM, (2008)Energy-speed exploration for very-wide range of dynamic V-F scaling., and . SBCCI, page 1-6. IEEE, (2013)