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Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC., , , , , , , and . IPDPS Workshops, page 452-459. IEEE, (2023)Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project., , , , , and . DATE, page 410-415. IEEE, (2017)Large Forests and Where to "Partially" Fit Them., , and . ASP-DAC, page 550-555. IEEE, (2022)A CAD-based methodology to optimize HLS code via the Roofline model., , , , , and . ICCAD, page 116:1-116:9. IEEE, (2020)Journal Track Paper ICFPT 2023 : Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs., , and . ICFPT, page 5. IEEE, (2023)Hardware Design Automation of Convolutional Neural Networks., , , , , and . ISVLSI, page 224-229. IEEE Computer Society, (2016)New Solution For a (Scaff)Old Problem: an FPGA Approach., , , , and . IPDPS Workshops, page 75-78. IEEE, (2023)Tiramisu: A Polyhedral Compiler for Expressing Fast and Portable Code., , , , , , , , and . CGO, page 193-205. IEEE, (2019)OXiGen: A Tool for Automatic Acceleration of C Functions Into Dataflow FPGA-Based Kernels., , , and . IPDPS Workshops, page 91-98. IEEE Computer Society, (2018)A Unified Backend for Targeting FPGAs from DSLs., , , and . ASAP, page 1-8. IEEE Computer Society, (2018)