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TGPA: tile-grained pipeline architecture for low latency CNN inference.

X. Wei, Y. Liang, X. Li, C. Yu, P. Zhang, and J. Cong. ICCAD, page 58. ACM, (2018)

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Xuechao Xing

Wei Wei

Other publications of authors with the same name

ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.C. Bai, J. Huang, X. Wei, Y. Ma, S. Li, H. Zheng, B. Yu, and Y. Xie. MICRO, page 268-282. ACM, (2023)FlexBFS: a parallelism-aware implementation of breadth-first search on GPU.G. Liu, H. An, W. Han, X. Li, T. Sun, W. Zhou, X. Wei, and X. Tang. PPoPP, page 279-280. ACM, (2012)Generating Systolic Array Accelerators With Reusable Blocks.L. Jia, L. Lu, X. Wei, and Y. Liang. IEEE Micro, 40 (4): 85-92 (2020)An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA.Z. Ma, T. Dai, X. Wei, and G. Luo. ACM Trans. Embed. Comput. Syst., 22 (6): 92:1-92:22 (November 2023)Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment.X. Wei, Y. Liang, P. Zhang, C. Yu, and J. Cong. FPGA, page 120. ACM, (2019)Distributed Control Independence for Composable Multi-processors.M. Mao, H. An, T. Sun, Q. Li, B. Deng, X. Wei, and J. Zhou. ACIS-ICIS, page 124-129. IEEE Computer Society, (2012)FTDL: An FPGA-tailored Architecture for Deep Learning Systems.R. Shi, Y. Ding, X. Wei, H. Liu, H. So, and C. Ding. FPGA, page 320. ACM, (2020)PetS: A Unified Framework for Parameter-Efficient Transformers Serving.Z. Zhou, X. Wei, J. Zhang, and G. Sun. USENIX Annual Technical Conference, page 489-504. USENIX Association, (2022)Frequency Improvement of Systolic Array-Based CNNs on FPGAs.J. Zhang, W. Zhang, G. Luo, X. Wei, Y. Liang, and J. Cong. ISCAS, page 1-4. IEEE, (2019)GNNear: Accelerating Full-Batch Training of Graph Neural Networks with near-Memory Processing.Z. Zhou, C. Li, X. Wei, X. Wang, and G. Sun. PACT, page 54-68. ACM, (2022)

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Disambiguation of "Wei, Xuechao"

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TGPA: tile-grained pipeline architecture for low latency CNN inference.

Please choose a person to relate this publication to

Xuechao Xing

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wei, Xuechao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML TGPA: tile-grained pipeline architecture for low latency CNN inference.

Please choose a person to relate this publication to

Xuechao Xing

Wei Wei

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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TGPA: tile-grained pipeline architecture for low latency CNN inference.