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The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors.

, , , и . IEEE PACT, стр. 155-164. IEEE Computer Society, (2002)

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José Manuel Coutinho e Castro

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Dagoberto Acacio Morón-León

Ursula E E Köhler

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Design of an efficient communication infrastructure for highly contended locks in many-core CMPs., , и . J. Parallel Distributed Comput., 73 (7): 972-985 (2013)Hardware transactional memory with software-defined conflicts., , , , , , , и . ACM Trans. Archit. Code Optim., 8 (4): 31:1-31:20 (2012)A Direct Coherence Protocol for Many-Core Chip Multiprocessors., , и . IEEE Trans. Parallel Distributed Syst., 21 (12): 1779-1792 (2010)Evaluating IA-32 web servers through simics: a practical experience., , и . J. Syst. Archit., 51 (4): 251-264 (2005)The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors., , , и . IEEE PACT, стр. 155-164. IEEE Computer Society, (2002)Efficient Dir0B Cache Coherency for Many-Core CMPs., , , и . ICCS, том 18 из Procedia Computer Science, стр. 2545-2548. Elsevier, (2013)A New Scalable Directory Architecture for Large-Scale Multiprocessors., , , и . HPCA, стр. 97-106. IEEE Computer Society, (2001)π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory., , , , и . HPCA, стр. 141-152. IEEE Computer Society, (2012)Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems., , , и . J. Supercomput., 68 (2): 914-934 (2014)Characterization of Conflicts in Log-Based Transactional Memory (LogTM)., , и . PDP, стр. 30-37. IEEE Computer Society, (2008)