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Disambiguation of "Egawa, Ryusuke"

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A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts.

, , , and . IEICE Trans. Inf. Syst., 96-D (9): 2047-2054 (2013)

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Ryusuke Shimada

Masashi Egawa

Yuko Egawa

Kazuko Pfeiffer-Egawa

 

Other publications of authors with the same name

Foreword., and . IEICE Trans. Electron., 106 (6): 301-302 (June 2023)A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs., , , and . MEDEA@PACT, page 113-120. ACM, (2007)Modeling of cache access behavior based on Zipf's law., , , and . MEDEA@PACT, page 9-15. ACM, (2008)Performance Evaluation of a Next-Generation SX-Aurora TSUBASA Vector Supercomputer., , , , , , and . ISC, volume 13948 of Lecture Notes in Computer Science, page 359-378. Springer, (2023)Design of a 3-D stacked floating-point adder., , and . 3DIC, page 1-4. IEEE, (2013)Improving the Accuracy in SpMV Implementation Selection with Machine Learning., , , , and . CANDAR (Workshops), page 172-177. IEEE, (2020)A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm., , , , and . ITCC (1), page 572-578. IEEE Computer Society, (2004)A media-oriented vector architectural extension with a high bandwidth cache system., , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2012)A cache partitioning mechanism to protect shared data for CMPs., , , , and . COOL Chips, page 1-2. IEEE Computer Society, (2016)Peachy Parallel Assignments (EduHPC 2019)., , , , , , , , , and 2 other author(s). EduHPC@SC, page 75-83. IEEE, (2019)