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Другие публикации лиц с тем же именем

DEFCON: Defect Acceleration through Content Optimization., , , , и . ITC, стр. 298-304. IEEE, (2022)A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays., , , , и . ATS, стр. 187-192. IEEE Computer Society, (2015)A defect tolerance framework for improving yield., , и . DAC, стр. 847-852. ACM, (2022)Every test makes a difference: Compressing analog tests to decrease production costs., , и . ASP-DAC, стр. 539-544. IEEE, (2016)Scalable and efficient analog parametric fault identification., , , и . ICCAD, стр. 387-392. IEEE, (2013)HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators., , , , , и . ISQED, стр. 457-462. IEEE, (2021)SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts., , , , , , , и . ITC, стр. 1-10. IEEE, (2020)Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults., , , , , и . ATS, стр. 120-125. IEEE, (2022)On Accelerating Path Delay Fault Simulation of Long Test Sequences., , , , и . ITC, стр. 1-9. IEEE Computer Society, (2008)Fast eye diagram analysis for high-speed CMOS circuits., , , , и . DATE, стр. 1377-1382. ACM, (2015)