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Smart Temperature Sensor for Thermal Testing of Cell-Based ICs.

, , , and . DATE, page 464-465. IEEE Computer Society, (2005)

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Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs., , , and . DATE, page 1271-1276. EDA Consortium, San Jose, CA, USA, (2007)GHz Testing and Its Fuzzy Targets., and . ITC, page 1228. IEEE Computer Society, (2002)CMOS IC nanometer technology failure mechanisms., , and . CICC, page 605-611. IEEE, (2003)On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor., , , and . IOLTW, page 87-91. IEEE Computer Society, (2000)Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories., , , , and . IOLTS, page 141-146. IEEE Computer Society, (2010)Using stochastic logic for efficient pattern recognition analysis., , , and . IJCNN, page 1057-1061. IEEE, (2008)Compact Static Power Model of Complex CMOS Gates., , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 348-354. Springer, (2005)A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates., and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 51-59. Springer, (2003)Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell., , , , and . LATS, page 1-6. IEEE Computer Society, (2015)CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing., , , and . ITC, page 719-726. IEEE Computer Society, (2003)