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Disambiguation of "Inaba, Hiromi"

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25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.

, , , , , , , , , , , and . ISCAS, page 1-4. IEEE, (2017)

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Hiromi Shirai

Jiro Inaba

Masayuki Inaba

Hiromi Ishibashi

Hiromi Habata

 

Other publications of authors with the same name

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS., , , , , and . MWSCAS, page 904-907. IEEE, (2013)Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS., , , , and . ISOCC, page 261-262. IEEE, (2016)36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector., , , , , , , and . ISOCC, page 61-62. IEEE, (2016)25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS., , , , , , , , , and 2 other author(s). ISCAS, page 1-4. IEEE, (2017)A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (5): 1288-1295 (2015)A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops., , , , , , and . ISCAS, page 2704-2707. IEEE, (2014)Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system., , , , and . ISOCC, page 249-250. IEEE, (2016)Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control., , , , and . MWSCAS, page 602-605. IEEE, (2012)