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The Stanford HYDRA chip, , , , , and . IEEE MICRO Magazine, (March 2000)TAPE: a transactional application profiling environment., , , , , , , and . ICS, page 199-208. ACM, (2005)The Case for a Single-Chip Multiprocessor., , , , and . ASPLOS, page 2-11. ACM Press, (1996)Transactional Memory Coherence and Consistency., , , , , , , , , and . ISCA, page 102-113. IEEE Computer Society, (2004)Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software., , , , , and . IEEE Micro, 24 (6): 92-103 (2004)Author's retrospective for: improving the performance of speculatively parallel applications on the hydra CMP., , and . ICS 25th Anniversary, page 51-53. ACM, (2014)Improving the performance of speculatively parallel applications on the Hydra CMP., , and . International Conference on Supercomputing, page 21-30. ACM, (1999)Evaluation of Design Alternatives for a Multiprocessor Microprocessor., , and . ISCA, page 67-77. ACM, (1996)The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors., , and . ARVLSI, page 303-319. IEEE Computer Society, (1997)"Software Performance Tuning with the Apple CHUD Tools"., , , and . IISWC, page 1. IEEE Computer Society, (2006)