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Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.

, , , , and . Asian Test Symposium, page 32-39. IEEE Computer Society, (2004)

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Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory., , and . ITC, page 100-105. IEEE Computer Society, (1985)On-Chip Weighted Random Patterns.. J. Electron. Test., 13 (1): 41-50 (1998)Distributed BIST Architecture to Combat Delay Faults.. J. Electron. Test., 16 (4): 369-380 (2000)Memory Chip BIST Architecture.. Great Lakes Symposium on VLSI, page 384-. IEEE Computer Society, (1999)BIST Pretest of ICs: Risks and Benefits., , and . VTS, page 142-149. IEEE Computer Society, (2006)Skewed-Load Transition Test: Part 1, Calculus.. ITC, page 705-713. IEEE Computer Society, (1992)Scan-based transition test., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (8): 1232-1241 (1993)Partitioning of polynomial tasks: test generation, an example., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (11): 1465-1468 (1991)Delay Fault Testing: How Robust are Our Models?, , , , and . VTS, page 502-503. IEEE Computer Society, (1996)Salvaging test windows in BIST diagnostic.. VTS, page 416-425. IEEE Computer Society, (1997)