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Disambiguation of "Zaruba, Florian"

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11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.

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Hans Zaruba

Marc-Michael Zaruba

Florian Franz

Realzeittest von Fahrzeugsoftware-Komponenten. TU München, (2009)

Florian Klasovsky

Syntheseparameter-Reaktivitätsbeziehungen für neue Palladiumoxidkatalysatoren in feinchemischen Hydrierungen. TU Darmstadt, (2009)

Florian Engelhardt

Börsenprospekthaftung der Leitungsorgane von Emittenten in Deutschland und Schweden. TU Dresden, (2007)
 

Other publications of authors with the same name

A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing., , and . Hot Chips Symposium, page 1-24. IEEE, (2020)Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores., , , , , and . ISCAS, page 1-5. IEEE, (2021)Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra., , , , and . DATE, page 1787-1792. IEEE, (2021)A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range., , , , , and . ESSCIRC, page 263-266. IEEE, (2021)Banshee: A Fast LLVM-Based RISC-V Binary Translator., , , , and . ICCAD, page 1-9. IEEE, (2021)Energy-efficient high-performance computing.. ETH Zurich, Zürich, Switzerland, (2021)An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study., , , , , , and . VLSI-SoC, page 43-48. IEEE, (2018)The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology., and . CoRR, (2019)A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI., , , and . VLSI-SoC, page 95-98. IEEE, (2019)Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing., , and . IEEE Micro, 41 (2): 36-42 (2021)