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High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures.

P. Maniotis, S. Gitzenis, L. Tassiulas, and N. Pleros. SiPhotonics@HiPEAC, page 1-8. IEEE Computer Society, (2015)

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Blagoje Nikosavi

Nikos Green

Nikos Papamichail

Nikos Wallburger

Nikos Parlavantzas

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Sub-μs Latency High-Port Optical Packet Switch Fabrics for Disaggregated Computing: The Hipoλaos OPS Architecture.M. Moralis-Pegios, N. Terzenidis, G. Mourgias-Alexandris, K. Vyrsokinos, and N. Pleros. ICTON, page 1-4. IEEE, (2018)PhoxTroT - a European initiative toward low cost and low power photonic interconnects for data centres.A. Håkansson, T. Tekin, L. Brusberg, N. Pleros, C. Vyrsokinos, D. Apostolopoulos, R. Pitwon, A. Miller, K. Wang, D. Tulli and 5 other author(s). ICTON, page 1-5. IEEE, (2015)All-Optical Recurrent Neural Network with Sigmoid Activation Function.G. Mourgias-Alexandris, G. Dabos, N. Passalis, A. Tefas, A. Totovic, and N. Pleros. OFC, page 1-3. IEEE, (2020)All-optical digital network coding for very high-throughput mm-wave Fiber-Wireless networks.C. Mitsolidou, C. Vagionas, D. Tsiokos, K. Ramantas, A. Miliou, and N. Pleros. OFC, page 1-3. IEEE, (2016)Optical static RAM cell using a monolithically integrated InP Flip-Flop and wavelength-encoded signals.S. Pitris, C. Vagionas, G. Kanellos, R. Kisacik, T. Tekin, R. Broeke, and N. Pleros. OFC, page 1-3. IEEE, (2016)On-Chip Universal Linear Optics using a 4x4 Silicon Photonic Coherent Crossbar.G. Giamougiannis, M. Moralis-Pegios, A. Tsakyridis, N. Bamiedakis, D. Lazovsky, and N. Pleros. OFC, page 1-3. IEEE, (2023)A 10Gb/s All-Optical Match-line for optical Content Addressable Memory (CAM) Rows.G. Mourgias-Alexandris, C. Vagionas, A. Tsakyridis, P. Maniotis, and N. Pleros. OFC, page 1-3. IEEE, (2018)Optical RAM row access and column decoding for WDM-formatted optical words.C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos. OFC/NFOEC, page 1-3. IEEE, (2013)A Silicon Photonic Coherent Neuron with 10GMAC/sec processing line-rate.G. Mourgias-Alexandris, M. Moralis-Pegios, S. Simos, G. Dabos, N. Passalis, M. Kirtas, T. Rutirawut, F. Gardes, A. Tefas, and N. Pleros. OFC, page 1-3. IEEE, (2021)An Optimized Medium-Transparent MAC Protocol for Multi-Service FiWi 5G Transport Networks.G. Kalfas, M. Gatzianas, D. Palianopoulos, A. Mesodiakaki, C. Vagionas, R. Maximidis, A. Miliou, and N. Pleros. GLOBECOM, page 4146-4151. IEEE, (2023)

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Disambiguation of "Pleros, Nikos"

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URL
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DIN 1505
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High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures.

Please choose a person to relate this publication to

Blagoje Nikosavi

Nikos Green

Nikos Papamichail

Nikos Wallburger

Nikos Parlavantzas

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Pleros, Nikos"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures.

Please choose a person to relate this publication to

Blagoje Nikosavi

Nikos Green

Nikos Papamichail

Nikos Wallburger

Nikos Parlavantzas

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures.