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Performance and Programming Environment of a Combined GPU/FPGA Desktop.

, , , , , and . High Performance Computing Workshop (2), volume 24 of Advances in Parallel Computing, page 177-193. IOS Press, (2012)

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Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL., , and . Algorithms, 12 (8): 149 (2019)Cache Remapping to Improve the Performance of Tiled Algorithms., and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 998-1007. Springer, (2000)Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler., , , and . DELTA, page 142-147. IEEE Computer Society, (2008)Comparing and combining GPU and FPGA accelerators in an image processing context., , , , , and . FPL, page 1-4. IEEE, (2013)Partitioning and Labeling of Index Sets in DO Loops with Constant Dependence Vectors.. ICPP (2), page 139-144. Pennsylvania State University Press, (1989)0-271-00686-2.Visualizing the Impact of the Cache on Program Execution., , and . IV, page 336-341. IEEE Computer Society, (2001)Extracting the Parallelism in Program with Unstructured Control Statements., and . ICPADS, page 264-271. IEEE Computer Society, (1994)Performance and toolchain of a combined GPU/FPGA desktop (abstract only)., , , , , and . FPGA, page 274. ACM, (2013)Non-Uniform Dependences Partitioned by Recurrence Chains., and . ICPP, page 100-107. IEEE Computer Society, (2004)Empowering Parallel Computing with Field Programmable Gate Arrays.. PARCO, volume 36 of Advances in Parallel Computing, page 16-31. IOS Press, (2019)