( en | de | ru )

 

Disambiguation of "Chen, Liang-Gee"

Author of the publication

copydeleteadd this publication to your clipboard
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.

, , and . APCCAS (1), page 383-388. IEEE, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Liang Chen

Liang Chen

Liang Chen

Liang-chi Chen

Yen-liang Chen

 

Other publications of authors with the same name

Low-power multi-processor system architecture design for universal biomedical signal processing., , and . ISCAS, page 857-860. IEEE, (2013)Video Compression., and . Handbook of Signal Processing Systems, Springer, (2010)Encoder Hardware Architecture for HEVC., , and . High Efficiency Video Coding, Springer, (2014)Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor., , , and . EMBC, page 7091-7094. IEEE, (2011)Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC., , and . ICASSP (5), page 9-12. IEEE, (2004)Region-of-unpredictable determination for accelerated full-frame feature generation in video sequences., , and . VCIP, page 434-437. IEEE, (2014)Parallel global elimination algorithm and architecture design for fast block matching motion estimation., , and . ICASSP (5), page 153-156. IEEE, (2004)Memory efficient JPEG2000 architecture with stripe pipeline scheme., , , , and . ICASSP (5), page 1-4. IEEE, (2005)Line Buffer Wordlength Analysis for Line-Based 2-D DWT., , , and . ICASSP (3), page 924-927. IEEE, (2006)Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System., , , , and . ICASSP (2), page 97-100. IEEE, (2007)