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Другие публикации лиц с тем же именем

Model Checking Controllers with Predicate Inputs., и . VLSI Design, стр. 332-337. IEEE Computer Society, (2013)A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis., , и . VLSI Design, стр. 95-102. IEEE Computer Society, (2007)Formal Verification of Modules under Real Time Environment Constraints., , и . VLSI Design, стр. 103-108. IEEE Computer Society, (2004)Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection., , , и . VLSID, стр. 325-330. IEEE, (2023)ALAFA: Automatic Leakage Assessment for Fault Attack Countermeasures., , , , и . DAC, стр. 136. ACM, (2019)Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?, , , , , и . DATE, стр. 668-669. IEEE Computer Society, (2004)SAT based solutions for consistency problems in formal property specifications for open systems., , , , и . ICCAD, стр. 885-888. IEEE Computer Society, (2005)Formal verification coverage: computing the coverage gap between temporal specifications., , , , , , , и . ICCAD, стр. 198-203. IEEE Computer Society / ACM, (2004)CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications., , , и . ACM Trans. Design Autom. Electr. Syst., 28 (1): 9:1-9:32 (января 2023)Formal Verification of Security Policy Implementations in Enterprise Networks., , и . ICISS, том 5905 из Lecture Notes in Computer Science, стр. 117-131. Springer, (2009)