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Disambiguation of "Devadas, Srinivas"

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TARDIS: Timestamp based Coherence Algorithm for Distributed Shared Memory.

, and . CoRR, (2015)

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Vinay Devadas

Deepika Devadas

Srinivas Jagarlamudi

Srinivas Yarlanki

Girish Srinivas

 

Other publications of authors with the same name

A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines., , and . DAC, page 601-606. IEEE Computer Society Press, (1990)Approaches to Multi-level Sequential Logic Synthesis.. DAC, page 270-276. ACM Press, (1989)Brief Announcement: Practical Synchronous Byzantine Consensus., , , and . DISC, volume 91 of LIPIcs, page 41:1-41:4. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2017)Intel SGX Explained, and . Cryptology ePrint Archive: Report 2016/086, (January 2016)On the verification of sequential machines at differing levels of abstraction., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (6): 713-722 (1988)Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (1): 122-134 (1994)Synthesis of robust delay-fault-testable circuits: practice., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (3): 277-300 (1992)BDD-based synthesis of extended burst-mode controllers., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (9): 782-792 (1998)Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (3): 373-383 (1992)Computation of floating mode delay in combinational circuits: practice and implementation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (12): 1924-1936 (1993)