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A BIST scheme for RTL circuits based on symbolic testabilityanalysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (1): 111-128 (2000)A low overhead design for testability and test generation technique for core-based systems-on-a-chip., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (11): 1661-1676 (1999)Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs., and . IEEE Trans. Parallel Distributed Syst., 4 (8): 864-874 (1993)Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip., and . Int. J. Embed. Syst., 1 (1/2): 2-13 (2005)High-level macro-modeling and estimation techniques for switching activity and power consumption., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (4): 538-557 (2003)Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (3): 296-308 (2007)Variable-Pipeline-Stage Router., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (9): 1669-1682 (2013)Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture., , , , and . IEEE Trans. Computers, 70 (1): 45-56 (2021)Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems., and . IEEE Trans. Computers, 42 (7): 780-793 (1993)Smart Healthcare., , , and . Foundations and Trends in Electronic Design Automation, 12 (4): 401-466 (2018)