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Disambiguation of "Furuta, Jun"

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Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process.

, , , and . IOLTS, page 1-6. IEEE, (2019)

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Hirokiyo Furuta

Jun Jun Lu

Jun Yang

Jun Li

Jun Yang

 

Other publications of authors with the same name

Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm., , , and . A-SSCC, page 209-212. IEEE, (2011)An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer., , , and . IRPS, page 1-5. IEEE, (2019)Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters., , , and . IEICE Trans. Electron., 103-C (4): 144-152 (2020)Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process., , , and . IOLTS, page 1-5. IEEE, (2022)A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles., , , and . ASP-DAC, page 83-84. IEEE, (2011)Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process., , , and . ASICON, page 1-4. IEEE, (2019)SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation., , , , , and . ICICDT, page 72-75. IEEE, (2023)Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process., , , and . IOLTS, page 1-6. IEEE, (2019)Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation., , , and . ASICON, page 1-4. IEEE, (2019)Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS., , , , , and . ICICDT, page 1-4. IEEE, (2017)