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Disambiguation of "Onodera, Hidetoshi"

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A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing.

, , , , , and . ISVLSI, page 488-493. IEEE, (2020)

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Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies., , and . ASP-DAC, page 589-590. ACM, (2003)Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication., , and . MWSCAS, page 795-798. IEEE, (2017)A performance optimization method by gate sizing using statistical static timing analysis., and . ISPD, page 111-116. ACM, (2000)Analysis and comparison of XOR cell structures for low voltage circuit design., , and . ISQED, page 703-708. IEEE, (2013)Variation-aware Flip-Flop energy optimization for ultra low voltage operation., , , and . SoCC, page 17-22. IEEE, (2014)PVT2: process, voltage, temperature and time-dependent variability in scaled CMOS process., and . ICCAD, page 126. ACM, (2018)A power optimization method considering glitch reduction by gate sizing., , and . ISLPED, page 221-226. ACM, (1998)Statistical modeling of device characteristics with systematic fluctuation., and . ISCAS, page 437-440. IEEE, (2000)CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models., , and . IOLTS, page 1-6. IEEE, (2021)Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region., , and . SoCC, page 236-241. IEEE, (2020)