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Disambiguation of "Vrudhula, Sarma B. K."

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Combinational equivalence checking for threshold logic circuits.

, , and . ACM Great Lakes Symposium on VLSI, page 102-107. ACM, (2007)

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Sarma Siahaan

Hassan Rahim B K

Gerhard K B Alberti

Nima Sarmadi

Srikrishna Sarma

 

Other publications of authors with the same name

Statistical library characterization using arbitrary polynomial chaos., , and . LASCAS, page 1-4. IEEE, (2017)A fast, energy efficient, field programmable threshold-logic array., , and . FPT, page 300-305. IEEE, (2014)Fast and robust differential flipflops and their extension to multi-input threshold gates., , , and . ISCAS, page 822-825. IEEE, (2015)Statistical waveform and current source based standard cell models for accurate timing analysis., and . DAC, page 227-230. ACM, (2008)Throughput optimal task allocation under thermal constraints for multi-core processors., , , and . DAC, page 776-781. ACM, (2009)Combinational equivalence checking for threshold logic circuits., , and . ACM Great Lakes Symposium on VLSI, page 102-107. ACM, (2007)Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series., and . DSD, page 139-143. IEEE Computer Society, (2005)Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA., , , , and . FPL, page 1-8. IEEE, (2016)AU: Timing Analysis Under Uncertainty., , and . ICCAD, page 615-620. IEEE Computer Society / ACM, (2003)Minimizing area and power of sequential CMOS circuits using threshold decomposition., , and . ICCAD, page 605-612. ACM, (2012)