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S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications.

M. Wu, W. Ren, P. Chen, W. Zhao, Y. Jing, J. Ru, Z. Wang, Y. Ma, R. Huang, T. Jia, and L. Ye. CICC, page 1-2. IEEE, (2024)

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Ru Zhang

Ru Xie

Tomasz Ru

Ru Hao

Rü tü ahin

Other publications of authors with the same name

18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.G. Li, A. Garg, T. He, U. Singh, J. Zhang, L. Rao, C. Liu, M. Nazari, Y. Liu, Y. Liu and 9 other author(s). ISSCC, page 338-340. IEEE, (2024)20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.Z. Wang, L. Ye, H. Zhanq, J. Ru, H. Fan, Y. Wang, and R. Huang. ISSCC, page 314-316. IEEE, (2020)A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control.Y. Zhang, Y. You, W. Ren, X. Xu, L. Shen, J. Ru, R. Huang, and L. Ye. ISSCC, page 68-69. IEEE, (2023)An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications.Y. Jing, Z. Wang, L. Shen, Y. Zhang, P. Chen, J. Ru, and L. Ye. ISCAS, page 1-4. IEEE, (2023)Session 15 overview: RF PLLs: RF subcommittee.J. Ru, J. Choi, and P. Wambacq. ISSCC, page 244-245. IEEE, (2018)S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications.M. Wu, W. Ren, P. Chen, W. Zhao, Y. Jing, J. Ru, Z. Wang, Y. Ma, R. Huang, T. Jia and 1 other author(s). CICC, page 1-2. IEEE, (2024)A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC.H. Li, K. Du, Y. Bao, Y. Dong, J. Ru, H. Xiao, H. Zhang, Z. Wang, Y. Zhong, L. Shen and 2 other author(s). IEEE J. Solid State Circuits, 59 (2): 435-448 (February 2024)Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.Y. Zhang, C. Xue, X. Wang, T. Liu, J. Gao, P. Chen, J. Liu, L. Sun, L. Shen, J. Ru and 2 other author(s). ISSCC, page 184-186. IEEE, (2022)12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network.Z. Wang, L. Ye, Y. Liu, P. Zhou, Z. Tan, H. Fan, Y. Zhang, J. Ru, Y. Wang, and R. Huang. ISSCC, page 436-438. IEEE, (2021)30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing.Y. Liu, Y. Ma, N. Shang, T. Zhao, P. Chen, M. Wu, J. Ru, T. Jia, L. Ye, Z. Wang and 1 other author(s). ISSCC, page 484-486. IEEE, (2024)

BibSonomy

Disambiguation of "Ru, Jiayoon"