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Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks.

M. Wang, S. Oruganti, S. Xie, R. Kumar, S. Mathew, and J. Kulkarni. ESSCIRC, page 529-532. IEEE, (2022)

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Jaydeep Belapure

Jagadish Kulkarni

Praveen Kulkarni

Aniket Kulkarni

Suchita Kulkarni

Other publications of authors with the same name

A novel slope detection technique for robust STTRAM sensing.S. Motaman, S. Ghosh, and J. Kulkarni. ISLPED, page 7-12. IEEE, (2015)A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.J. Kulkarni, K. Kim, and K. Roy. ISLPED, page 171-176. ACM, (2007)30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing.Y. Wang, M. Yang, C. Lo, and J. Kulkarni. ISSCC, page 492-494. IEEE, (2024)Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks.M. Wang, V. Iyer, S. Xie, G. Li, S. Mathew, R. Kumar, M. Orshansky, A. Yilmaz, and J. Kulkarni. CICC, page 1-2. IEEE, (2021)Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation.R. Mehra, S. Nibhanupudi, and J. Kulkarni. DRC, page 1-2. IEEE, (2022)Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design.V. Saripalli, S. Datta, V. Narayanan, and J. Kulkarni. NANOARCH, page 45-52. IEEE Computer Society, (2011)Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices.J. Rohan, P. Zhuang, S. Nibhanupudi, S. Banerjee, and J. Kulkarni. DRC, page 103-104. IEEE, (2019)Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices.S. Nibhanupudi, D. Veksler, A. Roy, M. Coupin, K. Matthews, J. Warner, G. Bersuker, J. Kulkarni, and S. Banerjee. DRC, page 1-2. IEEE, (2022)Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks.M. Wang, S. Oruganti, S. Xie, R. Kumar, S. Mathew, and J. Kulkarni. ESSCIRC, page 529-532. IEEE, (2022)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.S. Kim, Y. Shih, K. Mazumdar, R. Jain, J. Ryan, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)

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Disambiguation of "Kulkarni, Jaydeep P."

Please choose a person to relate this publication to

Jaydeep Belapure

Jagadish Kulkarni

Praveen Kulkarni

Aniket Kulkarni

Suchita Kulkarni

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kulkarni, Jaydeep P."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks.

Please choose a person to relate this publication to

Jaydeep Belapure

Jagadish Kulkarni

Praveen Kulkarni

Aniket Kulkarni

Suchita Kulkarni

Other publications of authors with the same name

Disambiguation