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A linear fractional transform (LFT) based model for interconnect parametric uncertainty., , and . DAC, page 375-380. ACM, (2004)Uncertainty modeling of gate delay considering multiple input switching., , and . ISCAS (3), page 2457-2460. IEEE, (2005)Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (9): 1337-1347 (2010)A probabilistic analysis of pipelined global interconnect under process variations., , and . ASP-DAC, page 724-729. IEEE, (2006)Realizable parasitic reduction for distributed interconnects using matrix pencil technique., , , and . ASP-DAC, page 780-785. IEEE Computer Society, (2004)Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design., , and . DATE, page 758-763. IEEE Computer Society, (2005)NBTI aware workload balancing in multi-core systems., , , and . ISQED, page 833-838. IEEE Computer Society, (2009)Predicting Interconnect Uncertainty with a New Robust Model Order Reduction Method., and . ISQED, page 363-368. IEEE Computer Society, (2004)Stochastic analysis of interconnect performance in the presence of process variations., , and . ICCAD, page 880-886. IEEE Computer Society / ACM, (2004)Multipoint moment matching model for multiport distributed interconnect networks., , and . ICCAD, page 85-91. ACM / IEEE Computer Society, (1998)