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Disambiguation of "Raut, Gopal"

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Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture".

, , , and . IEEE Open J. Circuits Syst., (2021)

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Karappurath Gopalan

Kreshna Gopal

Gopal Mamdapurkar

Vijay Gopalakrishnan

Ram Gopal

 

Other publications of authors with the same name

A CORDIC Based Configurable Activation Function for ANN Applications., , , and . ISVLSI, page 78-83. IEEE, (2020)SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture., , , , , , , , , and 2 other author(s). ISVLSI, page 308-313. IEEE, (2022)A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators., , , and . ISQED, page 1-8. IEEE, (2024)In-Memory Computing with 6T SRAM for Multi-operator Logic Design., , , , and . Circuits Syst. Signal Process., 43 (1): 646-660 (January 2024)Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture"., , , and . IEEE Open J. Circuits Syst., (2021)Design and Analysis of Posit Quire Processing Engine for Neural Network Applications., , , , , and . VLSID, page 252-257. IEEE, (2023)An Ultra Low Power AES Architecture for IoT., , , , , and . VDAT, volume 1066 of Communications in Computer and Information Science, page 334-344. Springer, (2019)Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array., , and . ACM Great Lakes Symposium on VLSI, page 199-202. ACM, (2022)A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators., , , , and . IFIPIoT (1), volume 683 of IFIP Advances in Information and Communication Technology, page 433-441. Springer, (2023)Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications., , , , , , and . VDAT, volume 1066 of Communications in Computer and Information Science, page 655-663. Springer, (2019)