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Disambiguation of "Lim, Ji-Hoon"

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Inductor Design of Interleaved Totem-Pole Bridgeless Boost PFC Based on Pareto Optimization.

, , , , and . IECON, page 1-6. IEEE, (2023)

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Ji-Hoon Hong

Seong-Hoon Lim

Yun-Ji Lim

Ji-Young Lim

Christina Hoon

 

Other publications of authors with the same name

A Study on Markerless AR-Based Infant Education System Using CBIR., and . SUComS, volume 78 of Communications in Computer and Information Science, page 52-58. Springer, (2010)An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 43 (1): 121-131 (2008)Design of Cyber Attack Precursor Symptom Detection Algorithm through System Base Behavior Analysis and Memory Monitoring., , , , and . FGIT-FGCN (2), volume 120 of Communications in Computer and Information Science, page 276-283. Springer, (2010)One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique., , , and . ISOCC, page 513-516. IEEE, (2012)An Improved PWM Method of Inverter PFC for Non-Isolated OBC., , , , , , and . IECON, page 1-6. IEEE, (2023)Inductor Design of Interleaved Totem-Pole Bridgeless Boost PFC Based on Pareto Optimization., , , , and . IECON, page 1-6. IEEE, (2023)A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs., , , , , and . Journal of Circuits, Systems, and Computers, 20 (4): 741-756 (2011)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , and 19 other author(s). ISSCC, page 492-617. IEEE, (2007)A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (2): 141-145 (2016)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction., , , , , , , , , and 20 other author(s). ISSCC, page 434-435. IEEE, (2010)