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Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells., , , and . ICECS, page 581-584. IEEE, (2018)A MCU-robust Interleaved Data/Detection SRAM for Space Environments., , , , and . ISVLSI, page 1-6. IEEE, (2023)Process Variability Impact on the SET Response of FinFET Multi-level Design., , , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 89-113. Springer, (2019)Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit., , , , and . LASCAS, page 1-4. IEEE, (2021)Evaluation of SET under Process Variability on FinFET Multi-level Design., , , and . VLSI-SoC, page 179-184. IEEE, (2019)Circuit Level Design Methods to Mitigate Soft Errors., , , , and . LATS, page 1-3. IEEE, (2020)A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures., , , , , , and . SBCCI, page 1-6. IEEE, (2023)Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study., , , , , and . LATS, page 1-6. IEEE, (2021)Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters., , , and . LATS, page 1-6. IEEE, (2020)A Tool for Automatic Radiation-Hardened SRAM Layout Generation., , , , and . ICECS, page 1-4. IEEE, (2023)