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An efficient VLSI architecture for extended variable block sizes motion estimation., , and . SoCC, page 347-350. IEEE, (2010)A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications., , , and . ISCAS, page 1-4. IEEE, (2017)Multi-Label Classification of Fundus Images With EfficientNet., , , , and . IEEE Access, (2020)A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (10): 3787-3791 (October 2023)A Ternary Memristive Logic-in-Memory Design for Fast Data Scan., , , , , , and . ICTA, page 183-184. IEEE, (2021)All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations., , , , and . ICTA, page 150-151. IEEE, (2022)An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations., , , , , and . ISCAS, page 1-5. IEEE, (2023)High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory., , , and . ISCAS, page 1-4. IEEE, (2021)An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits., , , and . ISCAS, page 1-5. IEEE, (2021)An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits., , , and . ICCAD, page 1-9. IEEE, (2021)