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Disambiguation of "Juracy, Leonardo Rezende"

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XGT4: An industrial grade, open source tester for multi-gigabit networks.

, , , , and . ICECS, page 252-255. IEEE, (2017)

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Ana Juracy Harth

Fernando Ferreira Rezende

Ismael Rezende Lima

Leonardo Estupiñán

Leonardo Finocchi

 

Other publications of authors with the same name

An LSSD Compliant Scan Cell for Flip-Flops., , , , and . ISCAS, page 1-5. IEEE, (2018)Deploying Machine Learning in Resource-Constrained Devices for Human Activity Recognition., , and . SBESC, page 1-6. IEEE, (2023)Optimized Design of an LSSD Scan Cell., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 765-768 (2017)A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (12): 5171-5184 (2022)A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators., , , and . LASCAS, page 1-4. IEEE, (2021)Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template., , , and . SBCCI, page 1-6. IEEE, (2018)Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template., , , and . ASYNC, page 86-93. IEEE, (2020)XGT4: An industrial grade, open source tester for multi-gigabit networks., , , , and . ICECS, page 252-255. IEEE, (2017)On the reuse of timing resilient architecture for testing path delay faults in critical paths., , and . DATE, page 379-384. IEEE, (2018)A DfT Insertion Methodology to Scannable Q-Flop Elements., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (8): 1609-1612 (2018)