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Character of Graph Analysis Workloads and Recommended Solutions on Future Parallel Systems.

N. Tanabe, S. Tomimori, M. Takata, и K. Joe. ICA3PP (1), том 8285 из Lecture Notes in Computer Science, стр. 402-415. Springer, (2013)

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Noboru Yamazaki

Noboru Sonoyama

Noboru Hasegawa

Sergio Noboru Kuriyama

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Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY.N. Tanabe, T. Suzuoka, S. Nakamura, Y. Kawakura, и S. Oyanagi. ICPP (1), стр. 509-516. CRC Press, (1991)Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.A. Ohta, Y. Hamada, A. Kitamura, N. Tanabe, H. Amano, и H. Nakajo. PDPTA, стр. 787-793. CSREA Press, (2007)Acceleration for MPI derived datatypes using an enhancer of memory and network.N. Tanabe, и H. Nakajo. IPDPS Workshops, стр. 1-6. IEEE, (2010)Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.A. Kitamura, Y. Miyabe, T. Izawa, T. Miyashiro, K. Watanabe, T. Otsuka, H. Amano, Y. Hamada, N. Tanabe, и H. Nakajo. PDCAT, стр. 778-780. IEEE Computer Society, (2005)An Enhancer of Memory and Network for Cluster and its Applications.N. Tanabe, и H. Nakajo. PDCAT, стр. 99-106. IEEE Computer Society, (2008)On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.N. Tanabe, J. Yamamoto, H. Nishi, T. Kudoh, Y. Hamada, H. Nakajo, и H. Amano. ISPAN, стр. 186-194. IEEE Computer Society, (2000)A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.Y. Hamada, H. Nishi, A. Kitamura, N. Tanabe, H. Amano, и H. Nakajo. PDPTA, стр. 461-467. CSREA Press, (2005)Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.N. Tanabe, Y. Hamada, H. Nakajo, H. Imashiro, J. Yamamoto, T. Kudoh, и H. Amano. PARELEC, стр. 9-14. IEEE Computer Society, (2002)DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot.T. Miyashiro, A. Kitamura, H. Nakajo, и N. Tanabe. FPL, стр. 1-4. IEEE, (2006)The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing.N. Tanabe, M. Sasaki, H. Nakajo, M. Takata, и K. Joe. PDPTA, стр. 427-433. CSREA Press, (2009)

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