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Disambiguation of "Saxena, Saurabh"

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Large-Scale Evolution of Image Classifiers.

, , , , , , and . CoRR, (2017)

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Saurabh Sanatani

Abhinav Saxena

Saurabh Srivastava

Saurabh Bhavsar

Saurabh Ray

 

Other publications of authors with the same name

A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications., , , , and . VLSID, page 1-5. IEEE, (2023)A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter., , and . CICC, page 1-4. IEEE, (2013)A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW., , , and . CICC, page 1-4. IEEE, (2011)Quantifying the Impact of Prognostic Distance on Average Cost per Cycle., , , and . ICPHM, page 1-7. IEEE, (2019)A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUIrms Jitter and 0.98-1.06 mW/GHz in 65-nm CMOS., and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3714-3718 (2022)Architectural & circuit level techniques to improve energy efficiency of high speed serial links. University of Illinois Urbana-Champaign, USA, (2015)A Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process., , , , and . ISCAS, page 2740-2744. IEEE, (2022)A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter., , , , and . CICC, page 1-4. IEEE, (2015)A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2306-2320 (2017)15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS., , , , and . ISSCC, page 272-273. IEEE, (2014)